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» Evaluating CMPs and Their Memory Architecture
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ANCS
2010
ACM
13 years 5 months ago
sNICh: efficient last hop networking in the data center
: sNICh: Efficient Last Hop Networking in the Data Center Kaushik Kumar Ram, Jayaram Mudigonda, Alan L. Cox, Scott Rixner, Partha Ranganathan, Jose Renato Santos HP Laboratories H...
Kaushik Kumar Ram, Jayaram Mudigonda, Alan L. Cox,...
DAC
2008
ACM
14 years 8 months ago
On the role of timing masking in reliable logic circuit design
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
Smita Krishnaswamy, Igor L. Markov, John P. Hayes
PDP
2009
IEEE
14 years 2 months ago
PsycoTrace: Virtual and Transparent Monitoring of a Process Self
PsycoTrace is a set of tools to protect a process P from attacks that alter P self as specified by its source code. P self is specified in terms of legal traces of system calls ...
Fabrizio Baiardi, Dario Maggiari, Daniele Sgandurr...
QEST
2006
IEEE
14 years 1 months ago
Modeling Fiber Delay Loops in an All Optical Switch
We analyze the effect of a few fiber delay loops on the number of deflections in an all optical packet switch. The switch is based on the ROMEO architecture developed by Alcatel...
Ana Busic, Mouad Ben Mamoun, Jean-Michel Fourneau
HICSS
2000
IEEE
124views Biometrics» more  HICSS 2000»
13 years 11 months ago
An Empirical Study of Distribution based on Voyager: A Performance Analysis
The paper describes the model, implementation and experimental evaluation of a distributed Kohonen Neural Network application (Kohonen Application). The aim of this research is to...
Sérgio Viademonte, Frada Burstein, Fá...