501 search results - page 88 / 101 » Evaluating CMPs and Their Memory Architecture |
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
PLDI
2005
ACM
14 years 1 months ago
2005
ACM
Speculative parallelization can provide significant sources of additional thread-level parallelism, especially for irregular applications that are hard to parallelize by conventio...
ICS
2005
Tsinghua U.
14 years 1 months ago
2005
Tsinghua U.
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
MM
2004
ACM
14 years 1 months ago
2004
ACM
Stories make our experiences memorable over time. In constructing and sharing our personal and communal memories, we move in a reflective manner back and forth between our lifewor...
SAMOS
2004
Springer
14 years 29 days ago
2004
Springer
— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...