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ASAP
2007
IEEE
153views Hardware» more  ASAP 2007»
13 years 8 months ago
Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics
Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single system on chip (SoC) currently, and the number is likely to increase significa...
Haibo Zhu, Partha Pratim Pande, Cristian Grecu
IPCCC
2005
IEEE
14 years 1 months ago
Utilizing characteristics of last link to improve TCP performance
TCP, perhaps the most widely used transport protocol, was designed for wired links and stationary hosts. But more and more links with different characteristics are used to access...
Xiuchao Wu, I. Biswas, Mun Choon Chan, Akkihebbal ...
LCTRTS
2010
Springer
13 years 5 months ago
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin,...
PCRCW
1997
Springer
13 years 12 months ago
ChaosLAN: Design and Implementation of a Gigabit LAN Using Chaotic Routing
In recent years, theChaos Project at theUniversityofWashingtonhas analyzed and simulated a dozen routing algorithms. Three new routing algorithms have been invented; of these, the...
Neil R. McKenzie, Kevin Bolding, Carl Ebeling, Law...
INFOCOM
2009
IEEE
14 years 2 months ago
Path Diversity Aware Interdomain Routing
—As the Internet becomes the critical information infrastructure for both personal and business applications, fast and reliable routing protocols need to be designed to maintain ...
Feng Wang, Lixin Gao