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DATE
2007
IEEE
173views Hardware» more  DATE 2007»
14 years 4 months ago
Analytical router modeling for networks-on-chip performance analysis
Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largel...
Ümit Y. Ogras, Radu Marculescu
CASES
2007
ACM
14 years 1 months ago
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. ...
INFOCOM
2012
IEEE
12 years 12 days ago
Comparing alternative approaches for networking of named objects in the future Internet
Abstract—This paper describes and compares alternative architectures for achieving the functional goals of name oriented networking. The CCN (content-centric network) scheme prop...
Akash Baid, Tam Vu, Dipankar Raychaudhuri
SAMOS
2004
Springer
14 years 3 months ago
with Wide Functional Units
— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...
Miquel Pericàs, Eduard Ayguadé, Javi...
ICC
2007
IEEE
105views Communications» more  ICC 2007»
14 years 4 months ago
A QoS-Based Scheme for Planning and Dimensioning of Optical Label Switched Networks
— To support the growing demand for transmission, Optical Label Switching (OLS) technology seems to be attractive due to its ability to allow fast switching and Quality of Servic...
Yassine Khlifi, Noureddine Boudriga, Mohammad S. O...