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GLVLSI
2011
IEEE
344views VLSI» more  GLVLSI 2011»
13 years 1 months ago
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
Azam Seyedi, Adrià Armejach, Adrián ...
HPCA
2006
IEEE
14 years 10 months ago
DMA-aware memory energy management
As increasingly larger memories are used to bridge the widening gap between processor and disk speeds, main memory energy consumption is becoming increasingly dominant. Even thoug...
Vivek Pandey, Weihang Jiang, Yuanyuan Zhou, Ricard...
SIGCOMM
2004
ACM
14 years 3 months ago
Vivaldi: a decentralized network coordinate system
Large-scale Internet applications can benefit from an ability to predict round-trip times to other hosts without having to contact them first. Explicit measurements are often un...
Frank Dabek, Russ Cox, M. Frans Kaashoek, Robert M...
EAGC
2003
Springer
14 years 3 months ago
Decentralized vs. Centralized Economic Coordination of Resource Allocation in Grids
Application layer networks are software architectures that allow the provisioning of services requiring a huge amount of resources by connecting large numbers of individual compute...
Torsten Eymann, Michael Reinicke, Oscar Ardaiz, Pa...
INFOCOM
2002
IEEE
14 years 2 months ago
Fair Scheduling and Buffer Management in Internet Routers
Abstract—Input buffered switch architecture has become attractive for implementing high performance routers and expanding use of the Internet sees an increasing need for quality ...
Nan Ni, Laxmi N. Bhuyan