1304 search results - page 101 / 261 » Evaluating Hardware Compilation Techniques |
127
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ASAP
2007
IEEE
15 years 4 months ago
2007
IEEE
Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single system on chip (SoC) currently, and the number is likely to increase significa...
103
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FPL
2008
Springer
15 years 6 months ago
2008
Springer
This paper presents a fast and scalable method of computing signal toggle rate in FPGA-based circuits. Our technique is a vectorless estimation technique, which can be used in a C...
123
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JSA
2008
15 years 4 months ago
2008
Processor simulators are important parts of processor design toolsets in which they are used to verify and evaluate the properties of the designed processors. While simulating arch...
134
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ICS
2007
Tsinghua U.
15 years 10 months ago
2007
Tsinghua U.
Sensitivity Analysis (SA) is a novel compiler technique that complements, and integrates with, static automatic parallelization analysis for the cases when relevant program behavi...
156
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ASPDAC
2012
ACM
14 years 8 days ago
2012
ACM
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...