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» Evaluating Hardware Compilation Techniques
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154
Voted
ICCAD
2009
IEEE
121views Hardware» more  ICCAD 2009»
15 years 2 months ago
MOLES: Malicious off-chip leakage enabled by side-channels
Economic incentives have driven the semiconductor industry to separate design from fabrication in recent years. This trend leads to potential vulnerabilities from untrusted circui...
Lang Lin, Wayne Burleson, Christof Paar
162
Voted
QNS
1996
15 years 5 months ago
Real Inferno
Inferno is an operating system well suited to applications that need to be portable, graphical, and networked. This paper describes the fundamental oating point facilities of the...
Eric Grosse
CGO
2004
IEEE
15 years 8 months ago
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan d...
133
Voted
ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
15 years 2 months ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen
CODES
2005
IEEE
15 years 10 months ago
Enhanced code density of embedded CISC processors with echo technology
Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even ...
Youfeng Wu, Mauricio Breternitz Jr., Herbert H. J....