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» Evaluating Hardware Compilation Techniques
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HPCA
2002
IEEE
16 years 5 months ago
Improving Value Communication for Thread-Level Speculation
Thread-Level Speculation (TLS) allows us to automatically parallelize general-purpose programs by supporting parallel execution of threads that might not actually be independent. ...
J. Gregory Steffan, Christopher B. Colohan, Antoni...
ASPDAC
2009
ACM
110views Hardware» more  ASPDAC 2009»
15 years 11 months ago
A software solution for dynamic stack management on scratch pad memory
Abstract— In an effort to make processors more power efficient scratch pad memory (SPM) have been proposed instead of caches, which can consume majority of processor power. Howe...
Arun Kannan, Aviral Shrivastava, Amit Pabalkar, Jo...
DATE
2008
IEEE
156views Hardware» more  DATE 2008»
15 years 11 months ago
Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications
Embedded systems are becoming increasingly complex. Besides the additional processing capabilities, they are characterized by high diversity of computational models coexisting in ...
Antonio Carlos Schneider Beck, Mateus B. Rutzig, G...
TCAD
2002
146views more  TCAD 2002»
15 years 4 months ago
Static scheduling of multidomain circuits for fast functional verification
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
Murali Kudlugi, Russell Tessier
SYSTOR
2009
ACM
15 years 11 months ago
Energy and performance evaluation of lossless file data compression on server systems
Data compression has been claimed to be an attractive solution to save energy consumption in high-end servers and data centers. However, there has not been a study to explore this...
Rachita Kothiyal, Vasily Tarasov, Priya Sehgal, Er...