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» Evaluating Hardware Compilation Techniques
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COMSWARE
2007
IEEE
15 years 11 months ago
BARAKA: A Hybrid Simulator of SANETs
— We present BARAKA, a new simulator for SANETs. The evaluation of algorithms developed for communication and co-operation in this context is usually accomplished separately. On ...
Thomas Halva Labella, Isabel Dietrich, Falko Dress...
MICRO
2007
IEEE
133views Hardware» more  MICRO 2007»
15 years 11 months ago
Revisiting the Sequential Programming Model for Multi-Core
Single-threaded programming is already considered a complicated task. The move to multi-threaded programming only increases the complexity and cost involved in software developmen...
Matthew J. Bridges, Neil Vachharajani, Yun Zhang, ...
ATVA
2007
Springer
226views Hardware» more  ATVA 2007»
15 years 11 months ago
Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver
This paper presents a bounded model checking algorithm for the verification of analog and mixed-signal (AMS) circuits using a satisfiability modulo theories (SMT) solver. The sys...
David Walter, Scott Little, Chris J. Myers
MICRO
2005
IEEE
107views Hardware» more  MICRO 2005»
15 years 10 months ago
Stream Programming on General-Purpose Processors
— In this paper we investigate mapping stream programs (i.e., programs written in a streaming style for streaming architectures such as Imagine and Raw) onto a general-purpose CP...
Jayanth Gummaraju, Mendel Rosenblum
MICRO
2002
IEEE
128views Hardware» more  MICRO 2002»
15 years 9 months ago
Compiler-directed instruction cache leakage optimization
Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consum...
Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut...