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» Evaluating Hardware Compilation Techniques
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MICRO
1994
IEEE
113views Hardware» more  MICRO 1994»
13 years 11 months ago
Static branch frequency and program profile analysis
: Program profiles identify frequently executed portions of a program, which are the places at which optimizations offer programmers and compilers the greatest benefit. Compilers, ...
Youfeng Wu, James R. Larus
ISCA
1993
IEEE
125views Hardware» more  ISCA 1993»
13 years 11 months ago
Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5
er uses an abstract machine approach to compare the mechanisms of two parallel machines: the J-Machine and the CM-5. High-level parallel programs are translated by a single optimi...
Ellen Spertus, Seth Copen Goldstein, Klaus E. Scha...
PLDI
2009
ACM
14 years 2 months ago
Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory
Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performa...
Mojtaba Mehrara, Jeff Hao, Po-Chun Hsu, Scott A. M...
OOPSLA
2007
Springer
14 years 1 months ago
Using hpm-sampling to drive dynamic compilation
All high-performance production JVMs employ an adaptive strategy for program execution. Methods are first executed unoptimized and then an online profiling mechanism is used to ...
Dries Buytaert, Andy Georges, Michael Hind, Matthe...
ISCA
2000
IEEE
134views Hardware» more  ISCA 2000»
14 years 2 days ago
Architectural support for scalable speculative parallelization in shared-memory multiprocessors
Speculative parallelization aggressively executes in parallel codes that cannot be fully parallelized by the compiler. Past proposals of hardware schemes have mostly focused on si...
Marcelo H. Cintra, José F. Martínez,...