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» Evaluating Hardware Compilation Techniques
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ASPLOS
2009
ACM
14 years 8 months ago
Capo: a software-hardware interface for practical deterministic multiprocessor replay
While deterministic replay of parallel programs is a powerful technique, current proposals have shortcomings. Specifically, software-based replay systems have high overheads on mu...
Pablo Montesinos, Matthew Hicks, Samuel T. King, J...
IEEEPACT
2007
IEEE
14 years 2 months ago
Architectural Support for the Stream Execution Model on General-Purpose Processors
There has recently been much interest in stream processing, both in industry (e.g., Cell, NVIDIA G80, ATI R580) and academia (e.g., Stanford Merrimac, MIT RAW), with stream progra...
Jayanth Gummaraju, Mattan Erez, Joel Coburn, Mende...
ISCA
1999
IEEE
95views Hardware» more  ISCA 1999»
14 years 16 hour ago
Memory Sharing Predictor: The Key to a Speculative Coherent DSM
Recent research advocates using general message predictors to learn and predict the coherence activity in distributed shared memory (DSM). By accurately predicting a message and t...
An-Chow Lai, Babak Falsafi
ISCA
2011
IEEE
365views Hardware» more  ISCA 2011»
12 years 11 months ago
Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees
Today’s chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specia...
Boris Grot, Joel Hestness, Stephen W. Keckler, Onu...
DATE
2009
IEEE
159views Hardware» more  DATE 2009»
14 years 2 months ago
Design and implementation of a database filter for BLAST acceleration
— BLAST is a very popular Computational Biology algorithm. Since it is computationally expensive it is a natural target for acceleration research, and many reconfigurable archite...
Panagiotis Afratis, Constantinos Galanakis, Euripi...