1304 search results - page 23 / 261 » Evaluating Hardware Compilation Techniques |
ICCD
2000
IEEE
14 years 4 months ago
2000
IEEE
In superscalar architectures, out-of-order issue mechanisms increase performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. Whil...
WCE
2007
13 years 8 months ago
2007
—Linear equations provide useful tools for understanding the behavior of a wide variety of phenomena— from science and engineering to social sciences. A number of techniques ha...
CHARME
2001
Springer
14 years 6 days ago
2001
Springer
We describe SAFL+: a call-by-value, parallel language in the style of ML which combines imperative, concurrent and functional programming. Synchronous channels allow communication ...
FPL
2001
Springer
14 years 6 days ago
2001
Springer
Designers of safety-critical VLSI systems are asking for effective tools for evaluating and validating their designs. Fault Injection is commonly adopted for this task, and its eff...
ASAP
2007
IEEE
13 years 9 months ago
2007
IEEE
This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...