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» Evaluating Hardware Compilation Techniques
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ISPD
2004
ACM
97views Hardware» more  ISPD 2004»
14 years 1 months ago
Implementation and extensibility of an analytic placer
Automated cell placement is a critical problem in VLSI physical design. New analytical placement methods that simultaneously spread cells and optimize wirelength have recently rec...
Andrew B. Kahng, Qinke Wang
ISCA
2010
IEEE
185views Hardware» more  ISCA 2010»
14 years 23 days ago
Dynamic warp subdivision for integrated branch and memory divergence tolerance
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
Jiayuan Meng, David Tarjan, Kevin Skadron
SIGMETRICS
2010
ACM
212views Hardware» more  SIGMETRICS 2010»
14 years 15 days ago
A mean field model of work stealing in large-scale systems
In this paper, we consider a generic model of computational grids, seen as several clusters of homogeneous processors. In such systems, a key issue when designing efficient job al...
Nicolas Gast, Bruno Gaujal
ICECCS
1998
IEEE
168views Hardware» more  ICECCS 1998»
13 years 12 months ago
The Architecture Tradeoff Analysis Method
This paper presents the Architecture Tradeoff Analysis Method (ATAM), a structured technique for understanding the tradeoffs inherent in design. This method was developed to provi...
Rick Kazman, Mark H. Klein, Mario Barbacci, Thomas...
DAC
1998
ACM
13 years 12 months ago
OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification
—Functional simulation is still the primary workhorse for verifying the functional correctness of hardware designs. Functional verification is necessarily incomplete because it i...
Farzan Fallah, Srinivas Devadas, Kurt Keutzer