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» Evaluating Hardware Compilation Techniques
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PLDI
1999
ACM
13 years 12 months ago
Cache-Conscious Structure Layout
Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency hav...
Trishul M. Chilimbi, Mark D. Hill, James R. Larus
VLDB
1999
ACM
145views Database» more  VLDB 1999»
13 years 12 months ago
DBMSs on a Modern Processor: Where Does Time Go?
Recent high-performance processors employ sophisticated techniques to overlap and simultaneously execute multiple computation and memory operations. Intuitively, these techniques ...
Anastassia Ailamaki, David J. DeWitt, Mark D. Hill...
CASES
2007
ACM
13 years 11 months ago
A low power front-end for embedded processors using a block-aware instruction set
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since inst...
Ahmad Zmily, Christos Kozyrakis
IOPADS
1996
100views more  IOPADS 1996»
13 years 9 months ago
ENWRICH a Compute-Processor Write Caching Scheme for Parallel File Systems
Many parallel scientific applications need high-performance I/O. Unfortunately, end-to-end parallel-I/O performance has not been able to keep up with substantial improvements in p...
Apratim Purakayastha, Carla Schlatter Ellis, David...
CADE
2009
Springer
14 years 2 months ago
Interpolant Generation for UTVPI
Abstract. The problem of computing Craig interpolants in SMT has recently received a lot of interest, mainly for its applications in formal verification. Efficient algorithms for ...
Alessandro Cimatti, Alberto Griggio, Roberto Sebas...