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» Evaluating Hardware Compilation Techniques
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ICCAD
2004
IEEE
100views Hardware» more  ICCAD 2004»
14 years 4 months ago
DynamoSim: a trace-based dynamically compiled instruction set simulator
Instruction set simulators are indispensable tools for the architectural exploration and verification of embedded systems. Different techniques have recently been proposed to spe...
Massimo Poncino, Jianwen Zhu
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
14 years 1 months ago
Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities
Traditionally, active power has been the primary source of power dissipation in CMOS designs. Although, leakage power is becoming increasingly more important as technology feature...
Po-Kuan Huang, Soheil Ghiasi
IEEEPACT
2005
IEEE
14 years 1 months ago
Compiler Directed Early Register Release
This paper presents a novel compiler directed technique to reduce the register pressure and power of the register file by releasing registers early. The compiler identifies regi...
Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abe...
ARC
2006
Springer
157views Hardware» more  ARC 2006»
13 years 11 months ago
PISC: Polymorphic Instruction Set Computers
We introduce a new paradigm in the computer architecture referred to as Polymorphic Instruction Set Computers (PISC). This new paradigm, in difference to RISC/CISC, introduces hard...
Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Won...
IPPS
2006
IEEE
14 years 1 months ago
Techniques supporting threadprivate in OpenMP
This paper presents the alternatives available to support threadprivate data in OpenMP and evaluates them. We show how current compilation systems rely on custom techniques for im...
Xavier Martorell, Marc González, Alejandro ...