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» Evaluating Hardware Compilation Techniques
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SASP
2008
IEEE
183views Hardware» more  SASP 2008»
14 years 2 months ago
Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor
Different approaches have been proposed over the years for automatically transforming High-Level-Languages (HLL) descriptions of applications into custom hardware implementations. ...
Alexandros Papakonstantinou, Deming Chen, Wen-mei ...
SAT
2005
Springer
142views Hardware» more  SAT 2005»
14 years 1 months ago
Optimizations for Compiling Declarative Models into Boolean Formulas
Advances in SAT solver technology have enabled many automated analysis and reasoning tools to reduce their input problem to a SAT problem, and then to use an efficient SAT solver ...
Darko Marinov, Sarfraz Khurshid, Suhabe Bugrara, L...
HPCA
1998
IEEE
13 years 12 months ago
Comparative Evaluation of Latency Tolerance Techniques for Software Distributed Shared Memory
A key challenge in achieving high performance on software DSM systems is overcoming their relatively large communication latencies. In this paper, we consider two techniques which...
Todd C. Mowy, Charles Q. C. Chan, Adley K. W. Lo
DATE
2008
IEEE
226views Hardware» more  DATE 2008»
14 years 2 months ago
A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation
Abstract— We present a general method to evaluate RF BuiltIn Self-Test (BIST) techniques during the design stage. In particular, the adaptive kernel estimator is used to construc...
Haralampos-G. D. Stratigopoulos, Jeanne Tongbong, ...
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
14 years 1 days ago
Hardware Synthesis from C/C++ Models
Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of f...
Giovanni De Micheli