Sciweavers

1304 search results - page 34 / 261
» Evaluating Hardware Compilation Techniques
Sort
View
IPPS
2003
IEEE
14 years 2 months ago
Loop Dissevering: A Technique for Temporally Partitioning Loops in Dynamically Reconfigurable Computing Platforms
This paper presents a technique, called loop dissevering, to temporally partitioning any type of loop presented in programming languages. The technique can be used in the presence...
João M. P. Cardoso
DATE
2005
IEEE
121views Hardware» more  DATE 2005»
14 years 2 months ago
C Compiler Retargeting Based on Instruction Semantics Models
Efficient architecture exploration and design of application specific instruction-set processors (ASIPs) requires retargetable software development tools, in particular C compil...
Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, ...
CGO
2009
IEEE
14 years 3 months ago
Automatic Feature Generation for Machine Learning Based Optimizing Compilation
Recent work has shown that machine learning can automate and in some cases outperform hand crafted compiler optimizations. Central to such an approach is that machine learning tec...
Hugh Leather, Edwin V. Bonilla, Michael O'Boyle
IWMM
1998
Springer
153views Hardware» more  IWMM 1998»
14 years 1 months ago
Compiler Support to Customize the Mark and Sweep Algorithm
Mark and sweep garbage collectors (GC) are classical but still very efficient automatic memory management systems. Although challenged by other kinds of systems, such as copying c...
Dominique Colnet, Philippe Coucaud, Olivier Zendra
DATE
2010
IEEE
197views Hardware» more  DATE 2010»
13 years 3 months ago
Compilation of stream programs for multicore processors that incorporate scratchpad memories
The stream processing characteristics of many embedded system applications in multimedia and networking domains have led to the advent of stream based programming formats. Several ...
Weijia Che, Amrit Panda, Karam S. Chatha