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» Evaluating Hardware Compilation Techniques
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PLDI
2010
ACM
14 years 16 days ago
DRFX: a simple and efficient memory model for concurrent programming languages
The most intuitive memory model for shared-memory multithreaded programming is sequential consistency (SC), but it disallows the use of many compiler and hardware optimizations th...
Daniel Marino, Abhayendra Singh, Todd D. Millstein...
MICRO
2000
IEEE
98views Hardware» more  MICRO 2000»
14 years 2 months ago
The store-load address table and speculative register promotion
Register promotion is an optimization that allocates a value to a register for a region of its lifetime where it is provably not aliased. Conventional compiler analysis cannot alw...
Matt Postiff, David Greene, Trevor N. Mudge
DAC
2011
ACM
12 years 10 months ago
Enforcing architectural contracts in high-level synthesis
We present a high-level synthesis technique that takes as input two orthogonal descriptions: (a) a behavioral architectural contract between the implementation and the user, and (...
Nikhil A. Patil, Ankit Bansal, Derek Chiou
IPPS
1997
IEEE
14 years 2 months ago
Enhancing Software DSM for Compiler-Parallelized Applications
Current parallelizing compilers for message-passing machines only support a limited class of data-parallel applications. One method for eliminating this restriction is to combine ...
Peter J. Keleher, Chau-Wen Tseng
IWOMP
2010
Springer
14 years 2 months ago
A ROSE-Based OpenMP 3.0 Research Compiler Supporting Multiple Runtime Libraries
OpenMP is a popular and evolving programming model for shared-memory platforms. It relies on compilers to target modern hardware architectures for optimal performance. A variety of...
Chunhua Liao, Daniel J. Quinlan, Thomas Panas, Bro...