Sciweavers

1304 search results - page 5 / 261
» Evaluating Hardware Compilation Techniques
Sort
View
CEC
2005
IEEE
14 years 1 months ago
Fast evolution of custom machine representations
Described are new approaches for evaluating computer program representations for use in automated search methodologies such as the evolutionary design of software. Previously, prog...
Lorenz Huelsbergen
IEEEPACT
2009
IEEE
14 years 2 months ago
Chainsaw: Using Binary Matching for Relative Instruction Mix Comparison
With advances in hardware, instruction set architectures are undergoing continual evolution. As a result, compilers are under constant pressure to adapt and take full advantage of...
Tipp Moseley, Dirk Grunwald, Ramesh Peri
FPL
2009
Springer
172views Hardware» more  FPL 2009»
14 years 8 days ago
Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
Nachiket Kapre, André DeHon
DSN
2005
IEEE
14 years 1 months ago
Checking Array Bound Violation Using Segmentation Hardware
The ability to check memory references against their associated array/buffer bounds helps programmers to detect programming errors involving address overruns early on and thus avo...
Lap-Chung Lam, Tzi-cker Chiueh
DATE
2006
IEEE
113views Hardware» more  DATE 2006»
14 years 1 months ago
An interprocedural code optimization technique for network processors using hardware multi-threading support
Sophisticated C compiler support for network processors (NPUs) is required to improve their usability and consequently, their acceptance in system design. Nonetheless, high-level ...
Hanno Scharwächter, Manuel Hohenauer, Rainer ...