1304 search results - page 69 / 261 » Evaluating Hardware Compilation Techniques |
149
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MICRO
1994
IEEE
15 years 8 months ago
1994
IEEE
Branch instructions are recognized as a major impediment to exploiting instruction level parallelism. Even with sophisticated branch prediction techniques, many frequently execute...
154
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MICRO
2000
IEEE
15 years 8 months ago
2000
IEEE
Functionality and performance of EPIC architectural features depend on extensive compiler support. Predication, one of these features, promises to reduce control flow overhead and...
129
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TVLSI
2008
15 years 4 months ago
2008
Recently, it has become possible to implement floating-point cores on field-programmable gate arrays (FPGAs) to provide acceleration for the myriad applications that require high-p...
149
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TC
1998
15 years 4 months ago
1998
—We evaluate three extensions to directory-based cache coherence protocols in shared-memory multiprocessors. These extensions are aimed at reducing the penalties associated with ...
139
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CODES
2009
IEEE
15 years 11 months ago
2009
IEEE
Kahn Process Networks is an appealing model of computation for programming and mapping applications onto multi-processor platforms. Autonomous processes communicate through unboun...