1304 search results - page 6 / 261 » Evaluating Hardware Compilation Techniques |
ICCD
2003
IEEE
14 years 4 months ago
2003
IEEE
Compiled simulation is a well known technique for improving the performance of instruction set simulators at the cost of compilation time. However the compilation time overhead ma...
ICCD
1993
IEEE
13 years 11 months ago
1993
IEEE
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
CHARME
2001
Springer
14 years 5 days ago
2001
Springer
Abstract. We survey the work done so far in the FLaSH project (Functional Languages for Synthesising Hardware) in which the core ideas are (i) using a functional language SAFL to d...
BCS
2008
13 years 9 months ago
2008
This paper describes our approaches to raise the level of abstraction at which hardware suitable for accelerating computationally-intensive applications can be specified. Field-Pr...
ISI
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. Trusted software execution, prevention of code and data tampering, authentication, and providing a secure environment for software are some of the most important security...