1304 search results - page 81 / 261 » Evaluating Hardware Compilation Techniques |
139
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DATE
2004
IEEE
15 years 8 months ago
2004
IEEE
The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting special hardware features. Due to the irregular arc...
120
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GECCO
2005
Springer
15 years 10 months ago
2005
Springer
Checking if microprocessor cores are fully functional at the end of the productive process has become a major issue. Traditional functional approaches are not sufficient when cons...
121
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IPPS
1999
IEEE
15 years 8 months ago
1999
IEEE
We present the ParAL system which compiles Matlab scripts into C programs with calls to a parallel run-time library. The novel feature of the compiler is the optimisation of array...
142
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CDES
2008
15 years 5 months ago
2008
- The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, prac...
119
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ISLPED
2004
ACM
15 years 10 months ago
2004
ACM
Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-...