1304 search results - page 88 / 261 » Evaluating Hardware Compilation Techniques |
109
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ASPDAC
2001
ACM
15 years 8 months ago
2001
ACM
Our earlier work for fast evaluation of power consumption of general cores in a system-on-a-chip described techniques that involved isolating high-level instructions of a core, me...
135
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ISMVL
2009
IEEE
15 years 11 months ago
2009
IEEE
For formal verification of hardware Satisfiability Modulo Theory (SMT) solvers are increasingly applied. Today’s state-of-the-art SMT solvers use different techniques like ter...
136
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DATE
2005
IEEE
15 years 10 months ago
2005
IEEE
This paper addresses error-resilience as the capability to tolerate bit-flips in a compressed test data stream (which is transferred from an Automatic Test Equipment (ATE) to the...
115
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DATE
2007
IEEE
15 years 10 months ago
2007
IEEE
Lasers can be used by hackers to situations to inject faults in circuits and induce security flaws. On-line detection mechanisms are classically proposed to counter such attacks, ...
133
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EH
1999
IEEE
15 years 8 months ago
1999
IEEE
High-level analog circuit design is a complex problem domain in which evolutionary search has recently produced encouraging results. However, little is known about how to best str...