1304 search results - page 97 / 261 » Evaluating Hardware Compilation Techniques |
160
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CGO
2007
IEEE
15 years 8 months ago
2007
IEEE
In profiling, a tradeoff exists between information and overhead. For example, hardware-sampling profilers incur negligible overhead, but the information they collect is consequen...
137
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HPCA
2009
IEEE
16 years 5 months ago
2009
IEEE
The Architectural Vulnerability Factor (AVF) of a hardware structure is the probability that a fault in the structure will affect the output of a program. AVF captures both microa...
151
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ISCA
2005
IEEE
15 years 10 months ago
2005
IEEE
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
128
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HIPEAC
2005
Springer
15 years 10 months ago
2005
Springer
Detecting and predicting a program’s execution phases are crucial to dynamic optimizations and dynamically adaptable systems. This paper shows that a phase can be associated with...
151
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FPGA
2010
ACM
16 years 1 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...