1304 search results - page 99 / 261 » Evaluating Hardware Compilation Techniques |
148
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ICECCS
2010
IEEE
15 years 4 months ago
2010
IEEE
Abstract—Transactional Memory (TM) is a promising technique that addresses the difficulty of parallel programming. Since TM takes responsibility for all concurrency control, TM ...
155
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CODES
2002
IEEE
15 years 9 months ago
2002
IEEE
In many embedded systems, existence of a data cache might influence the effectiveness of process scheduling policy significantly. Consequently, a scheduling policy that takes in...
145
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DATE
2007
IEEE
15 years 11 months ago
2007
IEEE
Loop unrolling is a well-known compiler optimization that can lead to significant performance improvements. When used in High Level Synthesis (HLS) unrolling can affect the contr...
119
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DAC
1992
ACM
15 years 8 months ago
1992
ACM
This paper describes a model for, and an implementation of, production-based synthesis of hardware description language (HDL) code in which the overall structure of the resultant ...
123
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ASPDAC
2008
ACM
15 years 6 months ago
2008
ACM
In this paper we describe load scheduling, a novel method that balances load among register files by residual resources. Load scheduling can reduce register pressure for clustered...