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» Evaluating kilo-instruction multiprocessors
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IEEEPACT
2009
IEEE
14 years 2 months ago
Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors
Translation Lookaside Buffers (TLBs) are a staple in modern computer systems and have a significant impact on overall system performance. Numerous prior studies have addressed TL...
Abhishek Bhattacharjee, Margaret Martonosi
IPPS
2006
IEEE
14 years 1 months ago
Helper thread prefetching for loosely-coupled multiprocessor systems
This paper presents a helper thread prefetching scheme that is designed to work on loosely-coupled processors, such as in a standard chip multi-processor (CMP) system and in an in...
Changhee Jung, Daeseob Lim, Jaejin Lee, Yan Solihi...
PRDC
2006
IEEE
14 years 1 months ago
Fault-Tolerant Partitioning Scheduling Algorithms in Real-Time Multiprocessor Systems
This paper presents the performance analysis of several well-known partitioning scheduling algorithms in real-time and fault-tolerant multiprocessor systems. Both static and dynam...
Hakem Beitollahi, Geert Deconinck
HASKELL
2005
ACM
14 years 1 months ago
Haskell on a shared-memory multiprocessor
Multi-core processors are coming, and we need ways to program them. The combination of purely-functional programming and explicit, monadic threads, communicating using transaction...
Tim Harris, Simon Marlow, Simon L. Peyton Jones
ICCD
2004
IEEE
107views Hardware» more  ICCD 2004»
14 years 4 months ago
Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor
In this work we propose a methodology for the accurate analysis of the power consumption of interprocessor communication in a MPSoC, and the construction of high-level power macro...
Mirko Loghi, Luca Benini, Massimo Poncino