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» Evaluating kilo-instruction multiprocessors
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SIGMETRICS
2005
ACM
156views Hardware» more  SIGMETRICS 2005»
14 years 1 months ago
Evaluating the impact of simultaneous multithreading on network servers using real hardware
This paper examines the performance of simultaneous multithreading (SMT) for network servers using actual hardware, multiple network server applications, and several workloads. Us...
Yaoping Ruan, Vivek S. Pai, Erich M. Nahum, John M...
HPCA
2009
IEEE
14 years 8 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
LCPC
2001
Springer
13 years 12 months ago
A Comparative Evaluation of Parallel Garbage Collector Implementations
While uniprocessor garbage collection is relatively well understood, experience with collectors for large multiprocessor servers is limited and it is unknown which techniques best ...
C. Richard Attanasio, David F. Bacon, Anthony Cocc...
ISCA
2007
IEEE
182views Hardware» more  ISCA 2007»
14 years 1 months ago
Configurable isolation: building high availability systems with commodity multi-core processors
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redunda...
Nidhi Aggarwal, Parthasarathy Ranganathan, Norman ...
HIPEAC
2010
Springer
14 years 4 months ago
Low-Overhead, High-Speed Multi-core Barrier Synchronization
Whereas efficient barrier implementations were once a concern only in high-performance computing, recent trends in core integration make the topic relevant even for general-purpos...
John Sartori, Rakesh Kumar