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DAC
2005
ACM
14 years 8 months ago
A low latency router supporting adaptivity for on-chip interconnects
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
Jongman Kim, Dongkook Park, Theo Theocharides, Nar...
ISCA
2007
IEEE
111views Hardware» more  ISCA 2007»
14 years 1 months ago
Express virtual channels: towards the ideal interconnection fabric
Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the per...
Amit Kumar 0002, Li-Shiuan Peh, Partha Kundu, Nira...
CLUSTER
2003
IEEE
14 years 25 days ago
Performance Analysis of Java Message-Passing Libraries on Fast Ethernet, Myrinet and SCI Clusters
The use of Java for parallel programming on clusters according to the message-passing paradigm is an attractive choice. In this case, the overall application performance will larg...
Guillermo L. Taboada, Juan Touriño, Ramon D...
PDPTA
2003
13 years 9 months ago
The Performance of Routing Algorithms under Bursty Traffic Loads
Routing algorithms are traditionally evaluated under Poisson-like traffic distributions. This type of traffic is smooth over large time intervals and has been shown not necessaril...
Jeonghee Shin, Timothy Mark Pinkston
ISCA
2008
IEEE
170views Hardware» more  ISCA 2008»
14 years 1 months ago
Polymorphic On-Chip Networks
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
Martha Mercaldi Kim, John D. Davis, Mark Oskin, To...