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ISPASS
2003
IEEE
14 years 9 hour ago
Accelerating private-key cryptography via multithreading on symmetric multiprocessors
Achieving high performance in cryptographic processing is important due to the increasing connectivity among today’s computers. Despite steady improvements in microprocessor and...
Praveen Dongara, T. N. Vijaykumar
PLDI
1996
ACM
13 years 11 months ago
A Reduced Multipipeline Machine Description that Preserves Scheduling Constraints
High performance compilers increasingly rely on accurate modeling of the machine resources to efficiently exploit the instruction level parallelism of an application. In this pape...
Alexandre E. Eichenberger, Edward S. Davidson
MICRO
1999
IEEE
110views Hardware» more  MICRO 1999»
13 years 11 months ago
Balance Scheduling: Weighting Branch Tradeoffs in Superblocks
Since there is generally insufficient instruction level parallelism within a single basic block, higher performance is achieved by speculatively scheduling operations in superbloc...
Alexandre E. Eichenberger, Waleed Meleis
MICRO
1998
IEEE
98views Hardware» more  MICRO 1998»
13 years 11 months ago
Task Selection for a Multiscalar Processor
The Multiscalar architecture advocates a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential...
T. N. Vijaykumar, Gurindar S. Sohi
CCGRID
2005
IEEE
13 years 8 months ago
The Composite Endpoint Protocol (CEP): scalable endpoints for terabit flows
We introduce the Composite Endpoint Protocol (CEP) which efficiently composes a set of transmission elements to support high speed flows which exceed the capabilities of a single...
Eric Weigle, Andrew A. Chien