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DATE
2006
IEEE
120views Hardware» more  DATE 2006»
14 years 1 months ago
System-level scheduling on instruction cell based reconfigurable systems
This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distribut...
Ying Yi, Ioannis Nousias, Mark Milward, Sami Khawa...
ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
13 years 11 months ago
Unconstrained Speculative Execution with Predicated State Buffering
Speculative execution is execution of instructions before it is known whether these instructions should be executed. Compiler-based speculative execution has the potential to achi...
Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masa...
PLDI
2000
ACM
13 years 12 months ago
Optimal instruction scheduling using integer programming
{ This paper presents a new approach to local instruction scheduling based on integer programming that produces optimal instruction schedules in a reasonable time, even for very la...
Kent D. Wilken, Jack Liu, Mark Heffernan
CAL
2005
13 years 7 months ago
On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor
Previous research on runahead execution took it for granted as a prefetch-only technique. Even though the results of instructions independent of an L2 miss are correctly computed d...
Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt
ISCAPDCS
2007
13 years 9 months ago
Evaluation of architectural support for speech codecs application in large-scale parallel machines
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
Naeem Zafar Azeemi