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IOPADS
1996
100views more  IOPADS 1996»
13 years 8 months ago
ENWRICH a Compute-Processor Write Caching Scheme for Parallel File Systems
Many parallel scientific applications need high-performance I/O. Unfortunately, end-to-end parallel-I/O performance has not been able to keep up with substantial improvements in p...
Apratim Purakayastha, Carla Schlatter Ellis, David...
IPPS
2000
IEEE
13 years 11 months ago
On the Scheduling Algorithm of the Dynamically Trace Scheduled VLIW Architecture
In a machine that follows the dynamically trace scheduled VLIW (DTSVLIW) architecture, VLIW instructions are built dynamically through an algorithm that can be implemented in hard...
Alberto Ferreira de Souza, Peter Rounce
ICDCS
1997
IEEE
13 years 11 months ago
Multi-threading and Remote Latency in Software DSMs
This paper evaluates the use of per-node multi-threading to hide remote memory and synchronization latencies in a software DSM. As with hardware systems, multi-threading in softwa...
Kritchalach Thitikamol, Peter J. Keleher
ISCA
2000
IEEE
93views Hardware» more  ISCA 2000»
13 years 10 months ago
Reconfigurable caches and their application to media processing
High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing...
Parthasarathy Ranganathan, Sarita V. Adve, Norman ...
PE
2007
Springer
118views Optimization» more  PE 2007»
13 years 6 months ago
Analysis and simulation of a content delivery application for vehicular wireless networks
We propose and analyze an information-sharing application for wireless intervehicular networks, called Infoshare. Infoshare leverages the broadcast nature of the wireless medium t...
Marco Fiore, Claudio Casetti, Carla-Fabiana Chiass...