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» Evaluation of CORDIC Algorithms for FPGA Design
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FPGA
2005
ACM
122views FPGA» more  FPGA 2005»
14 years 27 days ago
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
Yan Lin, Fei Li, Lei He
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
14 years 4 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He
FPGA
2006
ACM
129views FPGA» more  FPGA 2006»
13 years 11 months ago
Power-aware RAM mapping for FPGA embedded memory blocks
Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a ...
Russell Tessier, Vaughn Betz, David Neto, Thiagara...
FPGA
2009
ACM
233views FPGA» more  FPGA 2009»
14 years 2 months ago
FPCNA: a field programmable carbon nanotube array
Carbon nanotubes (CNTs), with their unique electronic properties, are promising materials for building nanoscale circuits. In this paper, we present a new CNT-based FPGA architect...
Chen Dong, Scott Chilstedt, Deming Chen
FCCM
2009
IEEE
169views VLSI» more  FCCM 2009»
14 years 2 months ago
RC-BLASTn: Implementation and Evaluation of the BLASTn Scan Function
BLASTn is a tool universally used by biologists to identify similarities between nucleotide based biological genome sequences. This report describes an FPGA based hardware impleme...
Siddhartha Datta, Parag Beeraka, Ron Sass