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ICPP
2009
IEEE
14 years 2 months ago
Bank-aware Dynamic Cache Partitioning for Multicore Architectures
Abstract—As Chip-Multiprocessor systems (CMP) have become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single c...
Dimitris Kaseridis, Jeffrey Stuecheli, Lizy K. Joh...
MICRO
2002
IEEE
128views Hardware» more  MICRO 2002»
14 years 10 days ago
Compiler-directed instruction cache leakage optimization
Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consum...
Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut...
DSN
2007
IEEE
14 years 1 months ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...
CBSE
2006
Springer
13 years 11 months ago
A Process for Resolving Performance Trade-Offs in Component-Based Architectures
Designing architectures requires the balancing of multiple system quality objectives. In this paper, we present techniques that support the exploration of the quality properties of...
Egor Bondarev, Michel R. V. Chaudron, Peter H. N. ...
SIGMETRICS
2002
ACM
13 years 7 months ago
Full-system timing-first simulation
Computer system designers often evaluate future design alternatives with detailed simulators that strive for functional fidelity (to execute relevant workloads) and performance fi...
Carl J. Mauer, Mark D. Hill, David A. Wood