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TOG
2008
145views more  TOG 2008»
13 years 8 months ago
Real-time KD-tree construction on graphics hardware
We present an algorithm for constructing kd-trees on GPUs. This algorithm achieves real-time performance by exploiting the GPU's streaming architecture at all stages of kd-tr...
Kun Zhou, Qiming Hou, Rui Wang 0004, Baining Guo
FCCM
2006
IEEE
195views VLSI» more  FCCM 2006»
14 years 2 months ago
A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)
This paper presents a hardware-optimized variant of the well-known Gaussian elimination over GF(2) and its highly efficient implementation. The proposed hardware architecture, we...
Andrey Bogdanov, M. C. Mertens
FPGA
2008
ACM
191views FPGA» more  FPGA 2008»
13 years 10 months ago
A hardware framework for the fast generation of multiple long-period random number streams
Stochastic simulations and other scientific applications that depend on random numbers are increasingly implemented in a parallelized manner in programmable logic. High-quality ps...
Ishaan L. Dalal, Deian Stefan
MICRO
1993
IEEE
128views Hardware» more  MICRO 1993»
14 years 19 days ago
Techniques for extracting instruction level parallelism on MIMD architectures
Extensive research has been done on extracting parallelism from single instruction stream processors. This paper presents some results of our investigation into ways to modify MIM...
Gary S. Tyson, Matthew K. Farrens
HPCA
2004
IEEE
14 years 9 months ago
Hardware Support for Prescient Instruction Prefetch
This paper proposes and evaluates hardware mechanisms for supporting prescient instruction prefetch--an approach to improving single-threaded application performance by using help...
Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wan...