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» Event-driven processor power management
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TC
2011
13 years 2 months ago
Energy Reduction in Consolidated Servers through Memory-Aware Virtual Machine Scheduling
—Increasing energy consumption in server consolidation environments leads to high maintenance costs for data centers. Main memory, no less than processor, is a major energy consu...
Jae-Wan Jang, Myeongjae Jeon, Hyo-Sil Kim, Heeseun...
ISPAN
2005
IEEE
14 years 1 months ago
Process Scheduling for the Parallel Desktop
Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power ma...
Eitan Frachtenberg
GLVLSI
2006
IEEE
119views VLSI» more  GLVLSI 2006»
14 years 1 months ago
Thermal analysis of a 3D die-stacked high-performance microprocessor
3-dimensional integrated circuit (3D IC) technology places circuit blocks in the vertical dimension in addition to the conventional horizontal plane. Compared to conventional plan...
Kiran Puttaswamy, Gabriel H. Loh
VEE
2006
ACM
102views Virtualization» more  VEE 2006»
14 years 1 months ago
A stackless runtime environment for a Pi-calculus
The Pi-calculus is a formalism to model and reason about highly concurrent and dynamic systems. Most of the expressive power of the language comes from the ability to pass communi...
Frédéric Peschanski, Samuel Hym
ISCA
2002
IEEE
91views Hardware» more  ISCA 2002»
14 years 19 days ago
Slack: Maximizing Performance Under Technological Constraints
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
Brian A. Fields, Rastislav Bodík, Mark D. H...