253 search results - page 47 / 51 » Event-driven processor power management |
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
RTAS
2008
IEEE
14 years 2 months ago
2008
IEEE
Interactive 3D games are now widely available on a variety of mobile devices for which battery-life is a major concern. Many of these devices support voltage/frequencyscalable pro...
DSN
2007
IEEE
14 years 2 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
ASPLOS
2010
ACM
13 years 11 months ago
2010
ACM
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
EUROPAR
2010
Springer
13 years 8 months ago
2010
Springer
Abstract. Traditional parallel programming methodologies for improving performance assume cache-based parallel systems. However, new architectures, like the IBM Cyclops-64 (C64), b...