253 search results - page 9 / 51 » Event-driven processor power management |
ISCAPDCS
2008
13 years 9 months ago
2008
This paper introduces a combination of models and proofs for optimal power management via Dynamic Frequency Scaling and Dynamic Voltage Scaling. The approach is suitable for syste...
CSREAESA
2003
13 years 9 months ago
2003
− This paper presents an efficient system level power saving method for DRAM with multiple power modes. The proposed method is based on the power aware scheduling algorithm that ...
IEEEPACT
2008
IEEE
14 years 2 months ago
2008
IEEE
The emergence of power as a first-class design constraint has fueled the proposal of a growing number of run-time power optimizations. Many of these optimizations trade-off power...
HPDC
2012
IEEE
11 years 10 months ago
2012
IEEE
Consider a multithreaded parallel application running inside a multicore virtual machine context that is itself hosted on a multi-socket multicore physical machine. How should the...
ICPP
2008
IEEE
14 years 2 months ago
2008
IEEE
A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, high-speed interface to increase the device density and ...