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» Evolutionary Approach to Test Generation for Functional BIST
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ITC
1996
IEEE
127views Hardware» more  ITC 1996»
13 years 11 months ago
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
Nur A. Touba, Edward J. McCluskey
ICCAD
1995
IEEE
120views Hardware» more  ICCAD 1995»
13 years 11 months ago
Pattern generation for a deterministic BIST scheme
Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic ...
Sybille Hellebrand, Birgit Reeb, Steffen Tarnick, ...
ISCAS
1999
IEEE
106views Hardware» more  ISCAS 1999»
13 years 12 months ago
Test pattern generation for width compression in BIST
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
Paulo F. Flores, Horácio C. Neto, K. Chakra...
MTV
2005
IEEE
138views Hardware» more  MTV 2005»
14 years 1 months ago
Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets
Microprocessor technology is increasingly used for many applications; the large market volumes call for cost containment in the production phase. Process yield for processor produ...
Paolo Bernardi, Ernesto Sánchez, Massimilia...
ATS
1998
IEEE
170views Hardware» more  ATS 1998»
13 years 12 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...