Pattern generation for a deterministic BIST scheme

Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic test sets at distinctly lower costs than previously known approaches. In this paper it is shown how this scheme can be supported during test pattern generation. The presented ATPG algorithm generates test sets which can be encoded very efficiently. Experiments show that the area required for synthesizing a BIST scheme that encodes these patterns is significantly less than the area needed for storing a compact test set. Furthermore, it is demonstrated that the proposed approach of combining ATPG and BIST synthesis leads to a considerably reduced hardware overhead compared to encoding a conventionally generated test set.

• Type: Conference
• Year: 1995
• Where: ICCAD
• Authors: Sybille Hellebrand, Birgit Reeb, Steffen Tarnick, Hans-Joachim Wunderlich
• Keywords: Built-in Self-test Scheme, Deterministic Test Sets, Hardware, ICCAD 1995, Test Set