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IEEEPACT
2006
IEEE
14 years 1 months ago
Two-level mapping based cache index selection for packet forwarding engines
Packet forwarding is a memory-intensive application requiring multiple accesses through a trie structure. The efficiency of a cache for this application critically depends on the ...
Kaushik Rajan, Ramaswamy Govindarajan
IEEEPACT
2006
IEEE
14 years 1 months ago
Overlapping dependent loads with addressless preload
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
Zhen Yang, Xudong Shi, Feiqi Su, Jih-Kwon Peir
ISCAS
2006
IEEE
162views Hardware» more  ISCAS 2006»
14 years 1 months ago
Silicon neurons that phase-lock
Abstract—We present a silicon neuron with a dynamic, active leak that enables precise spike-timing with respect to a time-varying input signal. Our neuron models the mammalian bu...
J. H. Wittig Jr., Kwabena Boahen
ASPDAC
2006
ACM
157views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Delay modeling and static timing analysis for MTCMOS circuits
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
Naoaki Ohkubo, Kimiyoshi Usami
ELPUB
2006
ACM
14 years 1 months ago
Modelling a Layer for Real-Time Management of Interactions in Web Based Distance Learning
In the last few years, the University of Aveiro, Portugal, has been offering several distance learning courses over the Web, using e-learning platforms. Experience showed that dif...
Carlos Sousa Pinto, Fernando M. S. Ramos