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FPL
2007
Springer
97views Hardware» more  FPL 2007»
14 years 1 days ago
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee
ASYNC
2004
IEEE
107views Hardware» more  ASYNC 2004»
13 years 12 months ago
Analog Micropipeline Rings for High Precision Timing
I use asynchronous FIFO stages that are connected in rings to generate and deliver highly precise timing signals. I introduce a Micropipeline FIFO control stage that oscillates at...
Scott Fairbanks, Simon W. Moore
ATVA
2004
Springer
138views Hardware» more  ATVA 2004»
13 years 12 months ago
Providing Automated Verification in HOL Using MDGs
While model checking suffers from the state space explosion problem, theorem proving is quite tedious and impractical for verifying complex designs. In this work, we present a veri...
Tarek Mhamdi, Sofiène Tahar
CAV
2004
Springer
108views Hardware» more  CAV 2004»
13 years 12 months ago
Functional Dependency for Verification Reduction
Abstract. The existence of functional dependency among the state variables of a state transition system was identified as a common cause of inefficient BDD representation in formal...
Jie-Hong Roland Jiang, Robert K. Brayton
EH
2004
IEEE
117views Hardware» more  EH 2004»
13 years 12 months ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...