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ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
14 years 4 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
ECBS
2009
IEEE
164views Hardware» more  ECBS 2009»
14 years 2 months ago
Semantically Enhanced Containers for Concurrent Real-Time Systems
Future space missions, such as Mars Science Laboratory, are built upon computing platforms providing a high degree of autonomy and diverse functionality. The increased sophisticat...
Damian Dechev, Peter Pirkelbauer, Nicolas Rouquett...
ISCAS
2008
IEEE
136views Hardware» more  ISCAS 2008»
14 years 2 months ago
Spatial-temporal consistent labeling for multi-camera multi-object surveillance systems
Abstract—For an intelligent multi-camera multi-object surveillance system, object correspondence across time and space is important to many smart visual applications. In this pap...
Jing-Ying Chang, Tzu-Heng Wang, Shao-Yi Chien, Lia...
IEEEPACT
2007
IEEE
14 years 2 months ago
Performance Portable Optimizations for Loops Containing Communication Operations
Effective use of communication networks is critical to the performance and scalability of parallel applications. Partitioned Global Address Space languages like UPC bring the pro...
Costin Iancu, Wei Chen, Katherine A. Yelick
ISCA
2007
IEEE
177views Hardware» more  ISCA 2007»
14 years 2 months ago
Adaptive insertion policies for high performance caching
The commonly used LRU replacement policy is susceptible to thrashing for memory-intensive workloads that have a working set greater than the available cache size. For such applica...
Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, ...