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ISSS
2000
IEEE
111views Hardware» more  ISSS 2000»
14 years 13 days ago
Systematic Data Reuse Exploration Methodology for Irregular Access Patterns
Efficient use of an optimized custom memory hierarchy to exploit temporal locality in the memory accesses on array signals can have a very large impact on the power consumption i...
Tanja Van Achteren, Rudy Lauwereins, Francky Catth...
DATE
2008
IEEE
131views Hardware» more  DATE 2008»
14 years 2 months ago
Parametric Throughput Analysis of Synchronous Data Flow Graphs
Synchronous Data Flow Graphs (SDFGs) have proved to be a very successful tool for modeling, analysis and synthesis of multimedia applications targeted at both single- and multiproc...
Amir Hossein Ghamarian, Marc Geilen, Twan Basten, ...
ARC
2007
Springer
152views Hardware» more  ARC 2007»
13 years 8 months ago
Statistical signal processing approaches to fault detection
: The parity space approach to fault detection and isolation (FDI) has been developed during the last twenty years, and the focus here is to describe its application to stochastic ...
Fredrik Gustafsson
MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
13 years 6 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
ICRA
2007
IEEE
160views Robotics» more  ICRA 2007»
14 years 2 months ago
Morphing Bus: A rapid deployment computing architecture for high performance, resource-constrained robots
— For certain applications, field robotic systems require small size for cost, weight, access, stealth or other reasons. Small size results in constraints on critical resources s...
Colin D'Souza, Byung Hwa Kim, Richard M. Voyles