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ATS
2005
IEEE
100views Hardware» more  ATS 2005»
14 years 10 days ago
Finite State Machine Synthesis for At-Speed Oscillation Testability
In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing...
Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, ...
ISCAS
2011
IEEE
278views Hardware» more  ISCAS 2011»
12 years 10 months ago
A programmable axonal propagation delay circuit for time-delay spiking neural networks
— we present an implementation of a programmable axonal propagation delay circuit which uses one first-order logdomain low-pass filter. Delays may be programmed in the 550ms rang...
Runchun Wang, Craig T. Jin, Alistair McEwan, Andr&...
ITC
1997
IEEE
107views Hardware» more  ITC 1997»
13 years 11 months ago
On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops
- An all-digital technique for the measurement of the jitter transfer function of charge-pump phase-locked loops is introduced. Input jitter may be generated using one of two metho...
Benoît R. Veillette, Gordon W. Roberts
DATE
2003
IEEE
120views Hardware» more  DATE 2003»
14 years 1 hour ago
Crosstalk Reduction in Area Routing
Interconnect delay dominates system delay in modern circuits, and with reduced feature sizes, coupling capacitance and signal crosstalk have become significant issues. By spacing...
Ryon M. Smey, Bill Swartz, Patrick H. Madden
ITC
2003
IEEE
120views Hardware» more  ITC 2003»
13 years 12 months ago
High Quality ATPG for Delay Defects
: The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture smalldistributed delay de...
Puneet Gupta, Michael S. Hsiao