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DATE
2000
IEEE
113views Hardware» more  DATE 2000»
13 years 11 months ago
Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits
We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficien...
Irith Pomeranz, Sudhakar M. Reddy
EH
2003
IEEE
138views Hardware» more  EH 2003»
13 years 12 months ago
Implementing Evolution of FIR-Filters Efficiently in an FPGA
Reconfigurable hardware devices make it possible to change the topology of electronic circuits at runtime. Using reconfigurable devices as a platform for Evolvable hardware (EHW) ...
Knut Arne Vinger, Jim Torresen
EH
2000
IEEE
123views Hardware» more  EH 2000»
13 years 11 months ago
The Test Vector Problem and Limitations to Evolving Digital Circuits
How do we know the correctness of an evolved circuit? While Evolutionary Hardware is exhibiting its effectiveness, we argue that it is very difficult to design a large-scale digit...
Kosuke Imamura, James A. Foster, Axel W. Krings
ICES
2000
Springer
140views Hardware» more  ICES 2000»
13 years 10 months ago
Evolving Cellular Automata for Self-Testing Hardware
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
AHS
2006
IEEE
133views Hardware» more  AHS 2006»
14 years 20 days ago
Gate-level Morphogenetic Evolvable Hardware for Scalability and Adaptation on FPGAs
Traditional approaches to evolvable hardware (EHW), in which the field programmable gate array (FPGA) configuration is directly encoded, have not scaled well with increasing cir...
Justin Lee, Joaquin Sitte