Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits

We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficient to achieve complete coverage of stuck-at faults, since these weights are sufficient to reproduce any specific test pattern. For sequential circuits, the weights we use are defined based on subsequences of a deterministic test sequence. Such weights allow us to reproduce parts of the test sequence, and help ensure that complete fault coverage would be obtained by the weighted test sequences generated.

• Type: Conference
• Year: 2000
• Where: DATE
• Authors: Irith Pomeranz, Sudhakar M. Reddy
• Keywords: DATE 2000, Hardware, Sequential Circuits, Test Sequences, Weighted Test Sequences