Sciweavers

502 search results - page 92 / 101
» Evolving Hardware on a Large Scale
Sort
View
MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
14 years 2 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
CLUSTER
2007
IEEE
14 years 1 months ago
Identifying energy-efficient concurrency levels using machine learning
Abstract-- Multicore microprocessors have been largely motivated by the diminishing returns in performance and the increased power consumption of single-threaded ILP microprocessor...
Matthew Curtis-Maury, Karan Singh, Sally A. McKee,...
DATE
2009
IEEE
171views Hardware» more  DATE 2009»
14 years 1 months ago
Physically clustered forward body biasing for variability compensation in nanometer CMOS design
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse consequences on design predictability and yield. A number of recent works have...
Ashoka Visweswara Sathanur, Antonio Pullini, Luca ...
CASES
2006
ACM
14 years 1 months ago
Improving the performance and power efficiency of shared helpers in CMPs
Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. One alterna...
Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi...
SIGMETRICS
1995
ACM
144views Hardware» more  SIGMETRICS 1995»
14 years 1 months ago
On Characterizing Bandwidth Requirements of Parallel Applications
Synthesizing architectural requirements from an application viewpoint can help in making important architectural design decisions towards building large scale parallel machines. I...
Anand Sivasubramaniam, Aman Singla, Umakishore Ram...