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» Executing Higher Order Logic
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DSD
2010
IEEE
149views Hardware» more  DSD 2010»
13 years 8 months ago
Low Latency Recovery from Transient Faults for Pipelined Processor Architectures
Abstract--Recent technology trends have made radiationinduced soft errors a growing threat to the reliability of microprocessors, a problem previously only known to the aerospace i...
Marcus Jeitler, Jakob Lechner
LPAR
2007
Springer
14 years 4 months ago
Zenon : An Extensible Automated Theorem Prover Producing Checkable Proofs
Abstract. We present Zenon, an automated theorem prover for first order classical logic (with equality), based on the tableau method. Zenon is intended to be the dedicated prover ...
Richard Bonichon, David Delahaye, Damien Doligez
ACL
1990
13 years 11 months ago
Multiple Underlying Systems: Translating User Requests into Programs to Produce Answers
A user may typically need to combine the strengths of more than one system in order to perform a task. In this paper, we describe a component of the Janus natural language interfa...
Robert J. Bobrow, Philip Resnik, Ralph M. Weisched...
PADS
1996
ACM
14 years 2 months ago
Conservative Circuit Simulation on Shared-Memory Multiprocessors
We investigate conservative parallel discrete event simulations for logical circuits on shared-memory multiprocessors. For a first estimation of the possible speedup, we extend th...
Jörg Keller, Thomas Rauber, Bernd Rederlechne...
HPCA
2004
IEEE
14 years 10 months ago
Understanding Scheduling Replay Schemes
Modern microprocessors adopt speculative scheduling techniques where instructions are scheduled several clock cycles before they actually execute. Due to this scheduling delay, sc...
Ilhyun Kim, Mikko H. Lipasti