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IPPS
1999
IEEE
14 years 2 months ago
DynBench: A Dynamic Benchmark Suite for Distributed Real-Time Systems
In this paper we present the architecture and framework for a benchmark suite that has been developed as part of the DeSiDeRaTa project. The proposed benchmark suite is representat...
Behrooz Shirazi, Lonnie R. Welch, Binoy Ravindran,...
MICRO
1999
IEEE
102views Hardware» more  MICRO 1999»
14 years 2 months ago
Evaluation of a High Performance Code Compression Method
Compressing the instructions of an embedded program is important for cost-sensitive low-power control-oriented embedded computing. A number of compression schemes have been propos...
Charles Lefurgy, Eva Piccininni, Trevor N. Mudge
EUROPAR
1999
Springer
14 years 2 months ago
Multi-stage Cascaded Prediction
Two-level predictors deliver highly accurate conditional branch prediction, indirect branch target prediction and value prediction. Accurate prediction enables speculative executio...
Karel Driesen, Urs Hölzle
FPGA
1999
ACM
142views FPGA» more  FPGA 1999»
14 years 2 months ago
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems
Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we addr...
Abdel Ejnioui, N. Ranganathan
GLVLSI
1998
IEEE
122views VLSI» more  GLVLSI 1998»
14 years 2 months ago
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...