453 search results - page 31 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
One of the major issues faced by the semiconductor industry today is that of reducing chip yields. As the process technologies have scaled to smaller feature sizes, chip yields ha...
CSC
2009
13 years 8 months ago
2009
Random walk simulation is employed in many experimental algorithmic applications. Efficient execution on modern computer architectures demands that the random walk be implemented t...
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could enable applications s...
TCAD
2010
13 years 2 months ago
2010
For real-time applications, it is necessary to estimate the worst-case performance early in the design process without actual hardware implementation. While the non-preemptive task...
SAMOS
2007
Springer
14 years 1 months ago
2007
Springer
— General purpose architectures are designed to offer average high performance regardless of the particular application that is being run. Performance and power inefficiencies a...